Integrated circuits are formed on appropriate substrate materials, such as semiconductor materials and the like, in and on which a plurality of circuit elements in the form of transistors, resistors, capacitors and the like are manufactured on the basis of the desired technology. The semiconductor industry has experienced great advances in terms of manufacturing techniques, process tools, metrology procedures, design strategies and the like. For example, integrated circuits comprising millions of transistors are currently available, thereby enabling the implementation of extremely complex functions into a single semiconductor device. One important aspect in fabricating complex integrated circuits has been the continuous reduction of the feature sizes of the circuit elements, wherein currently critical dimensions of 50 nm and less are realized in sophisticated circuits, such as CPUs (central processing units), complex memory devices and the like. Moreover, in addition to increasing the number of individual circuit elements by reducing the critical feature sizes, very different types of circuit elements are increasingly provided in the same semiconductor substrate, which offers the possibility of implementing a plurality of different functions into a single semiconductor device. Consequently, by combining various types of electronic circuits, such as control circuitry, power circuitry and the like, entire systems may be formed on a single chip.
For example, semiconductor devices comprising complex control functionality in combination with power circuitry are increasingly used in many fields are typically referred to as smart power applications, since a plurality of intelligent features may be implemented into the semiconductor device in order to ensure the proper operational behavior of critical circuit portions such as power transistors and the like, under any circumstances. For example, in addition to providing the required periphery for reliably operating a power transistor, additional sensors and monitor structures may be implemented in order to reduce the probability of device failures, which may be caused by non-predictable events, such as signal interference caused by electrical noise, over temperature situations, over voltage and over current situations, etc. In this manner, not only very complex circuit functions may be realized but also operation of the device may be controlled by device internal functional blocks, thereby contributing to superior reliability of integrated circuits. Consequently, specifically designed integrated circuits may be applied also in critical technological fields which require a high degree of failure immunity, such as automotive applications and the like.
Due to the advance in process technologies and material systems used for the fabrication of sophisticated semiconductor devices, the operational behavior of complex semiconductor devices may not only be determined by the semiconductor based circuit elements themselves, i.e., by transistors, resistors, capacitors and the like, but the wiring system or metallization system of the semiconductor device also represents an important component that significantly determines reliability and performance of the overall semiconductor device. For example, upon implementing fast logic circuitry on the basis of CMOS technology based on field effect transistors having a gate length of 100 nm and less, the switching speed of these transistors may no longer significantly represent the limiting factor of the overall performance of the logic circuitry. Rather, the metallization system may significantly contribute to the signal propagation delay and may thus represent the actual limiting factor in view of overall performance of complex semiconductor devices. Similarly, the metallization system associated with a power transistor has great influence on the finally obtained drive current and switching behavior.
Typically, a metallization system of a complex semiconductor device comprises a plurality of metallization layers or levels, which may be understood as layers including appropriately designed conductor portions, for instance in the form of metal lines and the like, which are embedded in appropriate dielectric material. Furthermore, the metallization system comprises a plurality of “vertical” interconnect structures, for instance referred to as vias, which provide the electrical connection between the individual stacked metallization layers. Due to the increased packing density of circuit elements in the semiconductor material of the semiconductor device, also the number of required electrical connections per unit area in the metallization system is increased, which is typically accomplished by reducing the lateral dimensions of the metal features and/or by providing an increased number of stacked metallization layers. Any of these design measures is, however, typically associated with an increase of parasitic parameters, such as parasitic resistance in the metallization system, the parasitic capacitance between closely spaced metal regions, parasitic inductance values and the like.
Consequently, new processes and material systems may typically be implemented in the metallization system in an attempt to further reduce any parasitic effects. For example, frequently highly conductive materials, such as copper, may be used so as to provide for superior performance in terms of conductivity and electromigration compared to, for instance, other well-established metals such as aluminium. Furthermore, the dielectric constant of the dielectric materials in the metallization layer may be reduced, for instance by using so-called low-k dielectric materials, for instance having a dielectric constant of 3.0 or less and the like, wherein any such additional measures may not only affect electrical performance of the metallization system but may also influence other factors such as heat dissipation capability, mechanical strength, electromigration behavior and the like.
Typically, several hundred individual production processes and metrology procedures are required for completing a moderately complex semiconductor device, each of which may itself represent a complex process wherein a typical overall process time from launching a semiconductor substrate into the semiconductor facility until obtaining a packaged semiconductor device may typically be in the range of several months. Hence, in view of economic constraints and taking into consideration these extended overall process times the verification of performance characteristics of a newly designed integrated circuit cannot exclusively rely on the fabrication of a dedicated test chip which may, after completely passing through the manufacturing process, be tested so as to identify any flaws in the overall design and the actual silicon implementation.
For these reasons, the design phase has increasingly gained in importance and actually represents a critical part of the overall manufacturing process, which may thus significantly affect the economic success of a newly designed semiconductor product that is to be placed on the market. During the design of the integrated circuit under consideration an appropriate geometric representation or layout of the various device layers are established on the basis of the specifications with respect to the electrical behavior of the circuit under consideration. Furthermore, other requirements to be met by the product are for instance the required silicon area in the semiconductor chip, which may also affect the layout, i.e. the geometric configuration of the various features in the device layers including the metallization layers of the semiconductor device. For example, a reduced chip area which may typically allow the processing of an increased number of semiconductor chips per each process step is typically associated with a more sophisticated technology, which in turn may affect the overall production costs, the reliability of the device, for instance in terms of heat dissipation capability, electrocmigration, and the like. Thus, many of the design requirements may represent a compromise between performance and cost considerations.
After the verification of the circuit function, for instance based on the circuit schematic, also a simulation of the behavior of the semiconductor device may be performed on the basis of the design data, i.e. the layout data or any other data correlated thereto, in combination with additional information, such as type of technology used and the like, in order to identify any failures or weaknesses of the current design of the integrated circuit under consideration, without actually requiring the fabrication of a dedicated test chip. Consequently, a plurality of analysis tools have been developed so as to provide a design framework with additional capabilities in order to identify critical factors of the current design status, thereby significantly reducing the time for establishing an appropriate redesign version of the product in order to compensate for at least some of the previously identified design errors. With the significant reduction and thus increase of the packing density of sophisticated integrated circuits, however, significant resources may be required, in particular for determining the operational behavior of the complex metallization system, which may be understood as a three-dimensional system including a plurality of objects which may have a more or less pronounced electrical, mechanical and thermal coupling to each other. For these reasons, powerful analysis tools have been developed in order to “simulate” the characteristics of metallization systems, for instance for determining parasitic parameters, such as resistance, capacitance, inductance and the like. For example, sophisticated analysis tools, which will also be referred to herein as simulation tools, are available from “Silicon Frontline”, in which for instance the current flow may be calculated for appropriately selected unit volumes in the metallization system on the basis of finite element techniques by solving the Laplace differential equations. Based on any such sophisticated simulation tools for determining the operational behavior of complex metallization systems, for instance the critical resistance of power devices, such as power MOS transistors and the like, may efficiently be determined for Smart Power applications in which the electrical performance of the power device is one dominant aspect of the semiconductor device. When using the sophisticated simulation tool, for instance the “Silicon Frontline” tool, the design engineer is confronted with a complex task in view of properly initializing the simulation tool on the basis of appropriate design data obtained by using a dedicated process design kit (PDK), in which the actual layout data and any other required data files have been generated on the basis of the basic schematic of the desired electronic circuit. That is, upon initializing the simulation tool the various data files and design data are identified in the computer system, in which the design framework is implemented and also the complete database for the integrated circuit under consideration is created and is appropriately addressed by the design engineer.
To this end, a configuration file is compiled in a proper manner so as to comply with the requirements of the simulation tool used. Thus, the configuration file includes the various access paths in order to access the required data files and the data base created for the subsequent simulation, while also the various initialization data for the actual physical simulation are entered into the configuration file, wherein all the information of the configuration file is provided on the basis of a specific format required by the simulation tool. Consequently, the complex flow for initializing the physical simulation of a complex metallization system may require significant efforts for the designer which may thus result, in addition to the need for increased manpower, in a high probability of creating additional errors in specifying input information for the extraction and simulation of critical parameters, such as the local resistance of complex metallization systems and the like.